MCP18480T-I/SS【PDF 37/64 页】IC HOT SWAP CTRLR -48V 20SSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录44

33页 34页 35页 36页 [37页]38页 39页 40页 41页

?2003 Microchip Technology Inc.

DS20091B-page 37

MCP18480

OVO

Overvoltage detect.

Typically for normal operation. This pin is tied to V

NEG

This feature allows the overvoltage detection input to monitor an over-

voltage condition across the power module. The voltage is sensed at

the drain of the external MOSFET. The voltage across the load is inter-

nally determined based upon:

" The voltage difference between system ground and the voltage

on the V

NEG

" The voltage difference between the drain of the external FET and

the voltage on the V

NEG

An external resistor divider network (R

OVO1

and R

OVO2

) is attached

between the drain of the external MOSFET and the V

NEG

pin (R

OVO1

is connected between the drain of the external MOSFET and the OVO

pin, while R

OVO2

is connected between the OVO pin and the V

NEG

pin).

When the voltage across the external MOSFET (source-to-drain)

equals system ground voltage (- V

NEG

+), the maximum desired load

voltage, the GATE pin is forced to the voltage on the V

NEG

(disabling the external MOSFET).

To detect Overvoltage on the board (instead of the load) directly,

connect the OVO pin to the V

NEG

pin.

PWRGOOD

Power Good indicator.

This state of the output is determined by four conditions. These are:

" Undervoltage

" Overvoltage

" Current Limit

" External FET is fully-enhanced (from DRAIN

pin on power-up)

PWRGOOD is a CMOS logic voltage (V

NEG

or V

NEG

+12V).

PWRGOOD is active when the device has completed power-up and

the system is neither in an Undervoltage or Overvoltage condition.

Connecting the R

ISET

pin to the V

NEG

pin configures the PWRGOOD

pin to be active high. Connecting the R

ISET

pin to the V

REF

pin config-

ures the PWRGOOD pin to be active low.

ENABLE

TTL Enable Gate driver.

Used to enable the GATE pin and assert the PWRGOOD pin. The

ENABLE pin is active-high and is internally pulled up to 5V. This pin is

pulled low by the user to clear the current limit latch when a current-

limit fault occurs with RESTART

high, or to disable the GATE pin.

H = Enable the GATE and PWRGOOD pins.

L = Disables the GATE pin, deasserts the PWRGOOD pin and clears

current limit latch.

When the ENABLE pin is high, fault conditions will disable the GATE

pin and deasserts the PWRGOOD pin.

TABLE 3-1:

MCP18480 PIN DESCRIPTIONS (CONTINUED)

Pin Name

Number

Direction

Buffer

Type

Description

SSOP

Legend: TTL = TTL compatible input

ST = Schmitt Trigger input with CMOS levels

I = Input

O = Output

P = Power

CMOS = CMOS-compatible input

A = Analog

D = Digital

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式